The present invention relates generally to an improvement of performance of a semiconductor device and more particularly to a semiconductor device of high bit density realized in a structure suited for achieving high stability and enhanced reliability.
The technique for realizing the semiconductor devices in the form of integrated circuits having high bit density has made remarkable progress in recent years. Suppose, by way of example, a MOS dynamic random access memory (hereinafter referred to as a DRAM in abbreviation). The MOS DRAM of 1 Mbits is manufactured on a mass production basis. A test chip of a 4-Mbit DRAM has already been reported. At the present state of the art, a 16-Mbit-DRAM is en route for development for practical applications. For realizing the semiconductor device of such high bit density, the size of the devices or elements constituting the semiconductor device as well as the size of wires must be made very small or fine in the range on the order of 0.5 .mu.m to 1 .mu.m. However, a great difficulty is encountered in fabricating such small (fine) devices or elements and wires accurately, giving rise to a problem that remarkable deviations can not be avoided. Taking the MOS DRAM as an example, the gate length and the threshold voltages which mainly determine the characteristics of the MOS transistors constituting the MOS DRAM will vary significantly in dependence on fluctuation in the device size and impurity concentration. Considering the changes in the supply voltage and the ambient temperature in the actual operating condition, the access time of the DRAM will vary in the range from first to third order of magnitude. Further, deviations due to the fabrication process condition exert significant influence to the reliability of the device. More specifically, degradation in the dielectric breakdown strength (dioxide breakdown strength) as well as degradation in the characteristics (due to hot carriers) occur as the result of implementation of the elements in small or minute size. Further, such characteristics concerning reliability of the device depend by and large on the dispersion in the implemented size.
As a hitherto known technique for improving the stability and reliability of the characteristics of the integrated semiconductor device, there is known a method of operating the on-chip elements by lowering the externally supplied voltage with the aid of an on-chip voltage limiter provided on the semiconductor device chip, as is disclosed in U.S. Pat. No. 4,482,985.
However, in the prior known techniques mentioned above, no consideration is paid to the influence of the conditions in the fabrication process condition and the operating condition to the electric characteristics and reliability, and thus it has been difficult to realize a semiconductor device of high stability and improved reliability.
Besides, because no consideration is made concerning the influence of the condition in the fabrication process, yield of products of satisfactory quality in a manufacturing on the mass production basis is low, giving rise to a problem that high manufacturing cost is involved.